Virtual memory is an elaborate illusion of infinite continuity built upon fragmented reality.
Lin Tao knelt in the southwestern side of the chamber, three paces from the intersection seam. In his left hand, his brass tuning fork rested against the palm of his hand. In his right, his land-mapper metal pen hovered over the chalk-marked probe tiles.
In a virtualized stonework, Lin Tao reviewed, the memory management unit must perform two-space-folding paging. The guest running system translates Guest Virtual Addresses to Guest Physical Addresses. Then, the host overseer-core translates Guest Physical Addresses to Host Physical Addresses using Extended Page Tables.
This nested translation came at a severe performance cost.
When a memory access hit the Translation Lookaside Buffer—the processor’s hardware cache for virtual-to-physical address mappings—the address resolved in a single clock cycle.
However, when a TLB miss occurred, the hardware had to perform a full page table walk. In an Extended Page Table environment. It turned a single guest virtual address could need up to twenty-four sequential memory reads as the processor crossed four levels of guest page tables and four levels of host nested page tables!
Lin Tao prepared to exploit that massive latency differential.
He struck the tuning fork against his iron boot heel. That brought the shaking stem against his cheekbone to start his sound pocket watch.
