A memory bus stall is a crack in the continuum of time.
Lin Tao stood ten paces from the northwestern corner, his land-mapper metal pen gripped tightly in his bandaged right hand. His left hand hovered near his inner lapel. There, the brass tuning fork rested against the warm flannel lining.
In modern processor microarchitecture, Lin Tao analyzed silently, when a CPU core requests data that is absent from all three cache levels, it must issue a DRAM read request across the external bus. The core execution units can’t proceed. They stall, waiting between one hundred and fifty and two hundred nanoseconds for the memory controller to respond.
During those two hundred nanoseconds, the processor pipeline was suspended in a fragile, unsafe state. Instructions were queued in the Reorder Buffer. Risky counts hovered uncommitted. And the Store Buffer held pending writes in an unchecked state.
To force the map point math to overflow into host memory, Lin Tao had to strike the corner seam at the exact nanosecond. Just then, the bus stalled.
He needed a trigger.
And outside the quarantine cage, that trigger was arriving.
Through the floor, the low-hum sound shakes were building to a crescendo. Tie Shan was no longer pacing his strikes at three-minute intervals. The giant had engaged the sky vanguard in nonstop, savage moving combat. The anvil was ringing every few seconds.
